1. Field of the Invention
The present invention relates to transistor design, construction and fabrication. More specifically, the present invention relates to the design of complementary metal-oxide semiconductor (CMOS) transistors for optimal hot carrier injection testing of same.
2. Description of the Related Art
CMOS transistors are widely used in applications requiring high-speed, low power digital circuits including microprocessors, memory devices and gate arrays. CMOS transistors are typically fabricated by bonding silicon dioxide layers on a silicon substrate. The silicon dioxide layers are selectively etched away with a plasma current to expose the silicon substrate. Exposed silicon on either side of a nonetched area is implanted with ions to create source and drain areas. A conductive layer is deposited on the nonexposed area to create a gate for the transistor. Additional conductive layers are disposed on the source and drain areas to provide electrical connection thereto. The conductive layers are separated by a dielectric material. Multiple layers of conductive material are also disposed elsewhere on the substrate to provide pads for external connection to the transistor. The pads are connected to the transistor by the conductive layers and the interlayer connections therebetween.
The pad, the conductive layers and and the interlayer connections therebetween act as an antenna and attract plasma current during fabrication. The plasma currents tunnel through the weakly bonded silicon dioxide layer into the silicon substrate. This damages the transistor, impedes its operation, and shortens its useful life.
Conventional transistor designs afford limited control over this problem. The prior approach to the problem has been to test for this tunnel-through with a "Hot Carrier Injection" (HCI) test. The HCI test involves an application of a ground connection to the source terminal and the substrate of a transistor while applying a voltage to the gate and drain terminals. If the current through the device drops below a predetermined threshold, failure of the device is indicated.
Unfortunately, the conventional transistor does not accurately simulate actual processing conditions. Accordingly, the test does not predict failure of certain transistors with a high degree of certainty.
Hence, there was a need in the art for a method for improving the reliability of CMOS transistors. Specifically, there was a need in the art for a system and technique for reducing the deleterious effects associated with plasma tunneling in the fabrication of transistors.
The need in the art was addressed by U.S. patent application entitled HOT CARRIER INJECTION TEST STRUCTURE AND TESTING TECHNIQUE FOR STATISTICAL EVALUATION, Ser. No. 08/340,138, filed Nov. 15, 1994, by N. Bui, and now abandoned, the teachings of which are incorporated herein by reference. However, there are certain practical limitations associated with the use of the Bui invention for individual CMOS devices. Individual CMOS devices are generally subjected to a number of tests in addition to those discussed in the Bui application. Some of these tests require that the source, gate and/or drain terminals be accessible and in some cases isolated from the terminals of other devices. Terminal isolation in the above-mentioned device may be impractical and expensive.
Thus, a need remains in the art for a system and technique for reducing the deleterious effects associated with plasma tunneling in the fabrication of transistors which is practical for the fabrication of devices suitable for applications other than testing applications per se.